Field of the Invention
The present application relates generally to the field of semiconductor device manufacturing.
Description of the Related Art
The continuous scaling of CMOS devices has increased process cost significantly, primarily due to the need for multiple patterning. To compensate for the rapid process cost increase and maintain a low cost per transistor, accelerated contact area scaling is required. This reduction in contact area raises an enormous challenge with respect to source/drain contact resistance in such devices, because contact resistance is inversely proportional to contact area.
Currently for FinFET devices, the contact structure can include Ti deposited by physical vapor deposition (PVD) followed by TiN deposited by atomic layer deposition (ALD) and W deposited by ALD or chemical vapor deposition (CVD) to fill the contact trench. PVD processes typically have poor step coverage and only deposit on top of the source/drain, which has a very limited contact area.
Metal silicides can be used as electrical contacts in integrated circuits. Typically silicides are formed by depositing a metal by a PVD process on top of silicon and annealing to induce a solid state reaction. Part of the silicon that is present in gate, source and/or drain structures can thus be converted into a low-resistivity metal silicide. However, the non-selective nature of this metal deposition process may require the addition of complicated patterning steps. This process is carried out to realize a conductive path with a low bulk resistivity on the one hand, and to ensure good contact resistance on the other hand. However, this reductive process can consume the source/drain substrate, leading to undesirable or degraded device performance, for example increased resistance due to a reduction in the contact area or device cross-section.